The chip of K565RU3G needs three power supplies and it is necessary to consider requirements for an order of inclusion and switching off of power supplies: the first include a source – 5B, and disconnect the last. This requirement is caused by that tension – 5B moves on a substrate (crystal) and if not to connect it the first, thermal breakdown can happen influence, even short-term, tension of two other sources to tension 5 and 12V in a crystal. The order of inclusion of two other supply voltages can be any.
RAMS carry out record, storage and reading of any binary information. It is the main device of memory of digital systems in which the programs defining process of the current information processing and an array of the processed data are stored. Modern digital systems of the RAM are under construction of special chips of memory which unite in the corresponding functional block.
The regeneration which is carried out on the described algorithm is called" transparent": it is imperceptible for the microprocessor and does not reduce the speed of processing of programs. A condition for application of this way is existence of time intervals between two any appeals of the microprocessor to the RAM, sufficient for carrying out one cycle of regeneration, i.e. regeneration at the appeal to the RAM module to one address.
Process of regeneration stops at the appeal of the microprocessor to the RAM, and the controler processes the requirement of the microprocessor. At the end of an address cycle the controler transfers the RAM block to the regeneration mode, continuing this process from the address on which it was interrupted.
The STORAGE, characteristic for DBIS produced on MDP-technology is high entrance ohmic resistance. When determining number Q of DBIS of the STORAGE loaded on the TTL-scheme the capacity of entrances of a chip of memory is considered generally.
Information transfer via the multiplexer when it is in not chosen state is forbidden (thus the way out is found in a condition of low level). Each of multiplexers has on four information entrances and the strobiruyushchy entrances of E.0 and E Two aresny entrances of SED1 and SED2 operate at the same time two multiplexers.
where: KM-the coefficient considering number of categories ENCORE STORAGES (if number of the categories nM =1, KM=0, differently KM =; KZ-the coefficient considering the STORAGE type (for ROM KZ=5, and for the KZ RAM =; E-information capacity the STORAGE ENCORE (in bits).
With a nominal frequency of the generator 18mgts duration of a step is equal 5 microsec. If to consider that on performance of one cycle of regeneration of chips of K565RU3G 370 nanoseconds are required, possibility of realization is obvious.
where: Ra-the power consumed by the RAM in the mode of reading, record; Ro-moshchnost consumed by the RAM in the storage mode; mr-quantity of lines in the RAM matrix; Tts.Min-minimalnoye time of a cycle of the appeal to the RAM module; Treg-period regenerations, the defining maximum interval of time between two addresses to each address for recovery of the stored information.
In chips of memory of dynamic type of the EP function carries out the electric condenser formed in MDP of structure. Information is presented in the charge form: existence of a charge on the condenser corresponds logical 1, absence - logically As preservation time is limited to the condenser of a charge, provide periodic recovery (regeneration) of the written-down information. Besides, the synchronization providing the demanded sequence of inclusions and switching off of functional knots is necessary for them.
K565RU3G chip information capacity 16kh1bit. In its block diagram (the appendix enter the store matrix containing 16384 elements of memory located on crossings of 128 lines and 128 columns, 128 amplifiers of reading and regeneration, decoders of lines and columns, a control unit, the device of input-output and the multiplex register of the address executed in one silicon crystal.